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IC89C54/58/64
IC89C54/58/64
CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 16/32/64-Kbytes of FLASH
FEATURES
* 80C52 based architecture * 16K/32K/64K Byte Flash Memory with fastpulse programming algorithm * 256 x 8 RAM * Three 16-bit Timer/Counters * Full duplex serial channel * Boolean processor * Four 8-bit I/O ports, 32 I/O lines * Memory addressing capability - 64K Program Memory and 64K Data Memory * Program memory lock - Lock bits (3) * Power save modes: - Idle and power-down * Eight interrupt sources * Most instructions execute in 0.3 s * CMOS and TTL compatible * Maximum speed: 40 MHz @ Vcc = 5V * Packages available: - 40-pin DIP - 44-pin PLCC - 44-pin PQFP
GENERAL DESCRIPTION
IC89C54, IC89C58, IC89C64 are members of ICSI embedded microcontroller family. The IC89C54/58/64 uses the same powerful instruction set, has the same architecture, and is pin-to-pin compatible with standard 80C52 controller devices. IC89C54/58/64 are just changed internal Flash size, other features are same as standard IC89C52. The IC89C54/58/64 contains a 16K/32K/64K x 8 Flash; a 256 x 8 RAM; 32 I/O lines for either multi-processor communications; I/O expansion or full duplex UART; three 16-bit timers/counters; an eight-source, two-priority-level, nested interrupt structure; and on chip oscillator and clock circuit. The IC89C54/58/64 can be expanded using standard TTL compatible memory.
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
Figure 1. IC89C54/58/64 Pin Configuration: 40-pin DIP
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
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IC89C54/58/64
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
41
INDEX P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17
6
5
4
3
2
1
44
43
42
40 39 38 37 36 35 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
TOP VIEW
18
19
20
21
22
23
24
25
26
27
28
WR/P3.6
XTAL2
XTAL1
GND
A8/P2.0
A9/P2.1
NC
A10/P2.2
A11/P2.3
Figure 2. IC89C54/58/64 Pin Configuration: 44-pin PLCC
2
A12/P2.4
RD/P3.7
P0.3/AD3
34 33 32 31 30 29
P1.0/T2
VCC
P1.4
P1.3
P1.2
NC
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P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 1 2 3 4 5 6 7 8 9 10 11 12
43
42
41
40
39
38
37
36
35
P0.3/AD3
P1.0/T2
P1.4
P1.3
P1.2
VCC
NC
34 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/Vpp NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
13
14
15
16
17
18
19
20
21
22
WR/P3.6
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
Figure 3. IC89C54/58/64 Pin Configuration: 44-pin PQFP
A12/P2.4
XTAL2
XTAL1
GND
RD/P3.7
NC
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IC89C54/58/64
16K/32K/64K MAIN CODE FLASH VCC
SFR BLOCK
256 BYTE RAM
VSS
ALE PSEN
PORT 2
P2[7:0]
CLOCK & TIMING
RST EA XTAL2 XTAL1
80C31 CPU CORE
P0[7:0]
PORT 0
PORT 1
TIMER 2
UART
INT0 TIMER 0
INT1 TIMER 1
PORT 3
P1[7:0]
P3[7:0]
Figure 4. IC89C54/58/64 Block Diagram
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Table 1. Detailed Pin Description Symbol ALE/PROG PDIP 30 PLCC 33 PQFP 27 I/O I/O Name and Function Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the Program Pulse input (PROG) during Flash programming.
External access enable: EA# must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA# is held high, the device executes from internal program memory unless the program counter contains an address grater than 3FFFH/7FFFH respecting to IC89C54/58 and the device always executes internal program memory in IC89C64. This is also receives the 12 V programming enable voltage (Vpp) during Flash programming, when 12 V programming is selected.
EA/VPP
31
35
29
I
P0.0-P0.7
39-32
43-36
37-30
I/O
Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s. Port 0 also receives the command and code bytes during memory program and verification, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pullups. Port 1 also receives the low-order address byte during memory program and verification. T2(P1.0) : Timer/counter 2 external count input. T2EX(P1.1): Timer/counter 2 trigger input. Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, port 2 pins that are externally pulled low will source current because of the internal pullups. Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses. In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses, port 2 emits the contents of the P2 special function register. Port 2 also receives the high-order address bits from A13 to A8 and some control signals during Flash programming and verification. P2.6, P2.7 are the control signals while the chip programs and erases. P2.6 is a program command strobe signal. P2.7 is a data output enable signal.
P1.0-P1.7
1-8
2-9
40-44
I/O
1 2 P2.0-P2.7 21-28
2 3 24-31
40 41 18-25
I I I/O
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Table 1. Detailed Pin Description (continued) Symbol P3.0-P3.7 PDIP 10-17 PLCC 11, 13-19 PQFP 5, 7-13 I/O I/O Name and Function Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally pulled low will source current because of the internal pullups. Port 3 also serves the special features, as listed below: 10 11 12 13 11 13 14 15 5 7 8 9 I O I I RxD (P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. Serve as A14 during memory program and verification. INT1 (P3.3): External interrupt. Serve as A15 during memory program and verification. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6):External data memory write strobe. Control signal during memory program, verification and erase. RD (P3.7): External data memory read strobe. Control signal during memory program, verification and erase. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.PSEN is an input control signal while memory program and verification. Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An internal resistor to VSS permits a power-on reset using only an external capacitor. A small internal resistor permits power-on reset using only a capacitor connected to VCC. RST is an input control signal during memory program and verification. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. Ground: 0V reference. Power Supply: This is the power supply voltage for operation.
14 15 16 17 PSEN 29
16 17 18 19 32
10 11 12 13 26
I I O O O
RST
9
10
4
I
XTAL 1 XTAL 2 GND Vcc
19 18 20 40
21 20 22 44
15 14 16 38
I O I I
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OPERATION DESCRIPTPION
The detail desription of the IC89C54/58/64 included in this desription are: * Memory Map and Registers * Flash Memory
Other informations refer to IC80C52/32 data sheet except flash memory.
MEMORY MAP AND REGISTERS
Table 1 shows program memory and data memory size versus three products. The IC89C54/58/64 series includes a standard IC80C32 and a 16K/32K/64K Flash Memory. The program memory and data memory access ranges are listed table 2. Table 2. Program memory and Data memory sizes Main Flash RAM Size
IC89C54 16K Bytes : [0H~3FFFH] 256 Bytes : [ 0-FFH] IC89C58 32K Bytes : [0H~7FFFH] 256 Bytes : [ 0-FFH] IC89C64 64K Bytes : [0H~FFFFH] 256 Bytes : [ 0-FFH]
FLASH MEMORY PROGRAMMING
The Flash architecture of IC89C54/58/64 is shown in Figure 5. IC89C54/58 include block 1 and lock bits block. The signature bytes are fixed value reside in MCU, they are read only. Block 2 resides in IC89C64 only.
0030H 0032H
3x8 bits Signature Bytes
0030H 0032H
3x8 bits Signature Bytes
0030H 0032H
3x8 bits Signature Bytes
0000H 16K Flash (Block 1) 3FFFH
0000H
0000H
32K Flash (Block 1) 60K Flash (Block 1)
7FFFH Dummy Address Dummy Address EFFFH F000H FFFFH
4K Flash (Block 2)
3 Lock Bits Falsh Cell
3 Lock Bits Falsh Cell
3 Lock Bits Falsh Cell
IC89C54
IC89C58
IC89C64
Figure 5. The Flash Architecture of IC89C54/58/64 Integrated Circuit Solution Inc.
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IC89C54/58/64
The IC89C54/58/64 provide the user with a direct flash memory access that can be used for programming into the flash memory without using the CPU. The direct flash memory access is entered using the External Host Mode. While the reset input (RST) is continually held active (high), if the PSEN pin is forced by an input with low state, the device enters the External Host Mode arming state at this time. The CPU core is stopped from running and all the chip I/O pins are reassigned and become flash memory access and control pins. At this time, the external host should initiate a "Read Signature Bytes" operation. After the completion of the "Read Signature Bytes" operation, the device is armed and enters the External Host Mode. After the device enters into the External Host Mode, the internal flash memory blocks are accessed through the re-assigned I/O port pins by an external host, such as a printed circuit board tester, a PC controlled development board or an MCU programmer. When the chip is in the external host mode, Port 0 pins are assigned to be the parallel data input and output pins. Port 1 pins are assigned to be the low order address bus signals for the internal flash memory (A0-A7). The first six bits of Port 2 pins (P2[0:5]) are assigned to be the upper order address bus signals for the internal flash memory (A8-A13) along with two of the Port 3 pins (P3.2 as A14 and P3.3 as A15). Two upper order Port 2 pins (P2.6 and P2. 7) and two upper order Port 3 pins (P3.6 and P3.7) along with RST, PSEN, PROG/ALE, EA pins are assigned as the control signal pins. The P3.4 is assigned to be the ready/ busy status signal, the P3.5 is assigned to be the timeout signal, which can be used for handshaking with the external host during a flash memory programming operation. The flash memory programming operation (Erase, Program, Verify, etc.) is internally self-timed and can be controlled by an external host asynchronously or synchronously. The insertion of an "arming" command prior to entering the External Host Mode by utilizing the "Read Signature Bytes" operation provides additional protection for inadvertent writes to the internal flash memory cause by a noisy or unstable system environment during the power-up or power unstable conditions. The External Host Mode uses hardware setup mode, which are decoded from the control signal pins, to facilitate the internal flash memory erase, test and programming process. The External Host Mode Commands are enabled on the falling edge of ALE/PROG. The list in Table 3 outlines all the setup conditions of normal mode. Before entering these written modes must have read 3 signature bytes.
Programming Interface
Some conditions must be satisfied before entering the programming mode. The conditions are listed in table 3. The interface-controlled signals are matched these conditions, then the IC89C54/58/64 will enter received command mode. The flash command is accepted by the flash command decoder in command received mode. The programming interface is listed in figure 6.
VCC
A7-A0
P1
VCC
A13-A8
P2.5-2.0
A15-A14
P3.3-3.2
IC89C54/58/64
10K
P0
D7-D0
H L PROG pulse 12V/H
RST PSEN ALE/PROG EA/VPP VSS
P3.4 P3.5 P2.6 P2.7 P3.6 P3.7
Ready/Busy Timeout P2.6 P2.7 P3.6 P3.7
Figure 6. IC89C52/54/64 External Host Programming Signals 8 Integrated Circuit Solution Inc.
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Table 3. Flash Programming Mode P3.7 P0[7:0] P1[7:0] P3[3:2] COM P2[5:0] HEX(3) Read Signature Byte H L H H L L L L DO AL AH 0 Chip Erase H L 12V/H H L L L X X X 1 Block 1 (2) Erase H L 12V/H L H L L X X X 2 Block 2 (2) Erase H L 12V/H L L H L X X X 4 Program Main code H L 12V/H L H H H DI AL AH E Program Lock Bit 1 H L 12V/H H H H H X X X F Program Lock Bit 2 H L 12V/H H H L L X X X 3 Program Lock Bit 3 H L 12V/H H L H L X X X 5 Verify Lock Bits H L H H H L L H DO[3:1] X X 9 Verify Main Code H L H H L L H H DO AL AH C 1. To read the signature bytes 30H, 31H, 32H are needed before any written command. To read signature bytes is needed after any new mode changed. This operation provides additional protection for inadvertent writes to the internal flash memory cause by a noisy or unstable system environment during the power-up or unstable power condition. If any unstable power condition has happened while written operation proceeds, to read signature bytes again will re-enable written command. (Power-on reset voltage is about 2.7V.) 2. Block 1 includes flash address from 0000H to 3FFFH in IC89C54, from 0000H to 7FFFH in IC89C58, from 0000H to EFFFH in IC89C64. Block 2 includes F000H to FFFFH. Block 2 is resident in IC89C64 only. 3. "COM HEX" presents the combination value of [P3.7, P3.6, P2.7, P2.6]. Mode(1) RST PSEN# PROG# EA# P2.6 P2.7 P3.6
Product Identification
The "Read Signature Bytes" command accesses the Signature Bytes that identify the device as IC89C54/58/64 and the manufacturer code. External programmers primarily use these Signature Bytes, shown in Table 4, in the selection of programming algorithms. The Read Signature Bytes command is selected by the byte code of 00h on P3[7:6] and P2[7: 6]. Manufacturer code of ICSI is "D5H" that reside in address 30H of signature. The flash memory sizes of MCU are shown in address 31H, code value 04H respect to 16K main flash memory, code value 08H respect to 32K main flash memory, code value 10H respect to 64K main flash memory. The address 32H value of signature byte respect to written operation VPP value, code value FFH respects to 12V and 55H respects to 5V. Table 4. Signature Bytes Information Addr 30H IC89C54 (VPP=12V) IC89C54 (VPP=5V) IC89C58 (VPP=12V) IC89C58 (VPP=5V) IC89C64 (VPP=12V) IC89C64 (VPP=5V) D5H D5H D5H D5H D5H D5H Addr 31H 04H 04H 08H 08H 10H 10H Addr 32H FFH 05H FFH 05H FFH 05H
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IC89C54/58/64
Arming Command
An arming command must take place before a Written Mode will be recognized by the IC89C54/58/64. This is to prevent accidental triggering of written operation due to noise or programmer error. The arming command is as follows: A Read Signature Bytes command is issued. This is actually a natural step for the programmer, but will also serve as the arming command. After the above sequence, all other Written Mode commands are enabled. Before the Read Signature Bytes command is received, all other Written Mode commands received are ignored. The IC89C54/8/64 will exit Written Mode if power off, so arming command is needed every power on for entering External Host Command Mode.
Flash Operation Status Detection (Ext. Host Handshake)
The IC89C54/58/64 provide two signals mean for an external host to detect the completion of a flash memory operation, therefore the external host can optimize the system Program or Erase cycle of the embedded flash memory. The end of a flash memory operation cycle (Erase or Program) can be detected by: 1) monitoring the Ready/Busy bit at Port 3.4; 2) monitoring the Timeout Polling bit at Port 3.5. The following two Program commands are for programming new data into the memory array. Selection of which Program command to use for programming will be dependent upon the desired programming field size. The Program commands will not enable if Lock Bit 2 or Lock Bit 3 is enabled on the selected memory block. The "Program Main Code" command program data into a single byte. Ports P0[0:7] are used for data in. The memory location is selected by P1[0:7], P2[0:5], and P3[2:3] (A0-A15). The "Verify Main Code" command allows the user to verify that the IC89C54/58/64 correctly performed an Erase or Program command. Ports P0[0:7] are used for data out. The memory location is selected by P1[0:7], P2[0:5], and P3 [2:3] (A0-A15). These commands will not enable if any lock bit is enabled on the selected memory block.
External Host Mode Commands
The following is a brief description of the commands. See Table 3 for all signal logic assignments for the External Host Mode Commands. The critical timing for all Erase and Program commands, is self-generated by the flash memory controller on-chip. The high-to-low transition of the PROG signal initiates the Erase and Program commands, which are synchronized internally. All the data in the memory array will be erased to FFH. Memory addresses that are to be programmed must be in the erased state prior to programming. There are two erase commands in IC89C64, Block 1 erase and Block 2 erase. Selection of the Erase command to use, prior to programming the device, will be dependent upon the contents already in the array and the desired programming field block. The "Chip Erase" command erases all bytes in both memory blocks (16K/32K/64K) of the IC89C54/58/64.This command ignores the "Lock bits" status and will erase the Security Byte. The "Chip Erase" command is selected by the byte code of 01H on P3[7:6] and P2[7:6]. The "Block 1 Erase" command erases all bytes in one of the memory blocks 1 (16/32/60K) of the IC89C54/58/64. The "Block 2 Erase" command erases all bytes in one of the memory blocks 2 (Address range is from F000H to FFFFH) of the IC89C64. These block erase commands will not enable if the Lock Bit 2 or Lock Bit 3 is enabled.
Ready/BUSY B
The progress of the flash memory programming can be monitored by the Ready/BUSY output signal. The Ready/ BUSY indicates whether an Embedded Algorithm in Written State Machine (WSM) is in progress or complete. The RY/ BY status is valid after the falling edge of the programming or erase controlled signal. If the output is low (Busy), the device is in an erasing/programming state with an internal verification. If the output is high, the device is ready to read data. While the RY/BY signal is at low level (Busy) and Timeout is high level, the programming or erasing procedure is failed.
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Timeout
Timeout indicates whether the program or erase time has exceeded a specified internal timer limit. Under these conditions Timeout go to high and Ready/BUSY remains a low. This is a failed condition that indicates the program or erase cycle was not successful completed. If there are any program or erase failure in erasing operation, Timeout go to high and Ready/BUSY remains low. It is cleared by any rising edge of written signal (like Program Main Code, Chip Erase, ...etc.). The time from written signal to Timeout=1 is re-initiated at every written signal's rising edge. It is high when the program or erase operations don't complete and have no newly written signal in the expected time. 1. Set RST to high and PSEN to low. 2. Raise EA High (either 12V or 5V). 3. Read the "Read Signature Bytes" command to ensure the correct programming algorithm. 4. Verify that the memory blocks for programming are in the erased state, FFH. If they are not erased, then erase them using the appropriate Erase command. 5. Set P2.6, P2.7, P3.6, P3.7 to a properly programming combination. 6. Select the memory location using the address lines (P1 [0:7], P2[0:5], P3[2:3]). 7. Present the data in on P0[0:7]. 8. Pulse ALE/PROG. 9. Wait for low to high transition on Ready/Busy(P3.4) or Timeout pin(P3.5). If Ready/Busy is from low to high, this address is programmed completely. If the Timeout signal is from low to high before Ready/Busy goes high, this byte is failed in programming. 10. Repeat steps 6~9 until programming is finished.
Programming a IC89C54/58/64
To program new data into the memory array, supply 5 volts to VDD and RST, and perform the following steps.
Lock bits Features
The IC89C54/58/64 provide three lock bits to protect the embedded program against software piracy. These three bytes are user programmable. The relation between lock bits status and protection type are listed in table 5.
Table 5. Lock Bits Features Program Lock bits LB1 1 2 U P LB2 U U LB3 U U No program lock feature enabled. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, #EA is sampled and latched on reset, and Data verification is disabled. ("Verify Signature Byte" and "Verify Lock Bits are still enabled.) 3 4 P P P P U P Protection Type
Same as 2, also further written operation of the Flash is disabled Same as 3, also external execution is disabled
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Absolute Maximum Ratings
Parameter Operating temperature under bias Storage temperature range Voltage on any other pin to VSS Power dissipation ( based on package heat transfer l imitations, not device power consumption) 1.5 W Rating 0 to +70 -65 to +125 -2.0 to +7.0 Unit C (1) C V (2)
Notes : 1. Operating temperature is for commercial product defined by this spec. 2. Minimum D.C. input voltage is -0.5 V. During transitions, inputs may undershoot, to -2.0 V for periods less than 20 ns. Maximum D.C. voltage on output pins is VCC+0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. Warning: Stressing the device beyond the "Absolute Maximum Rating" may cause permanent damage. This is stress rating only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability.
Operating Range
Commercial devices case temperature VCC supply voltage Oscillator frequency 0 to +70 C +4.5 to 5.5 V 3.5 to 40 MHz
Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC CHARACTERISTICS
(Ta=0C to 70C; VCC=5V+10%; VSS=0V ) Symbol VIL VIL1 VIH VIH1 VSCH+ VSCH- VOL(1) Parameter Input low voltage (All except EA) Input low voltage (EA) Input high voltage (All except XTAL 1, RST) Input high voltage (XTAL 1) RST positive schmitt-trigger threshold voltage RST negative schmitt-trigger threshold voltage Output low voltage (Ports 1, 2, 3) VOL1
(1)
Test conditions
Min -0.5 -0.5 0.2Vcc + 0.9 0.7Vcc 0.7Vcc 0
Max 0.2Vcc - 0.1 0.2Vcc - 0.3 Vcc + 0.5 Vcc + 0.5 Vcc + 0.5 0.3Vcc 0.3 0.45 1.0 0.3 0.45 1.0 -- -- -- -- -- -- -50 +10 -650 300
Unit V V V V V V V V V V V V V V V V V V A A A K
Iol = 100 A IOL = 1.6 mA IOL = 3.5 mA IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA IOH = -10 A Vcc = 4.5V-5.5V IOL = -25 A IOL = -60 A
-- -- -- -- -- -- 0.9Vcc 0.75Vcc 2.4 0.9Vcc 0.75Vcc 2.4 -- -10 -- 50
Output low voltage (Port 0, ALE, PSEN)
VOH
Output high voltage (Ports 1, 2, 3, ALE, PSEN)
VOH1
Output high voltage (Port 0, ALE, PSEN)
IOH = -80 A Vcc = 4.5V-5.5V IOH = -300 A IOH = -800 A
IIL ILI ITL RRST Note:
Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V Input leakage current (Port 0) Logical 1-to-0 transition current (Ports 1, 2, 3) RST pulldown resister 0.45V < VIN < Vcc VIN = 2.0V VIN=0v
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink greater than the listed test conditions.
2.The Icc test conditions are shown below. Minimum VCC for Power Down is 2 V.
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POWER SUPPLY CHARACTERISTICS
Symbol Icc Parameter Power supply current Active mode
(1)
Test conditions Vcc = 5.0V 12 MHz 16 MHz 20 MHz 24 MHz 32 MHz 40 MHz
Min -- -- -- -- -- -- -- -- -- -- -- -- --
Max 20 26 32 38 50 62 5 6 7.6 9 12 15 50
Unit mA mA mA mA mA mA mA mA mA mA mA mA A
Idle mode
12 MHz 16 MHz 20 MHz 24 MHz 32 MHz 40 MHz
Power-down mode
Note: 1. See Figures7,8,9, and 10 for Icc test conditiions.
VCC = 5V
Vcc Vcc RST Vcc Vcc P0
P0
Vcc Icc RST Vcc Vcc
Icc
NC CLOCK SIGNAL
XTAL2 XTAL1 GND
NC CLOCK SIGNAL
XTAL2 XTAL1 GND
EA
EA
Figure 7. Active Mode
Figure 8. Active Mode
Vcc Icc RST Vcc Vcc P0
NC
XTAL2 XTAL1 GND
EA
Figure 9. Active Mode
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Integrated Circuit Solution Inc.
MC009-0B
IC89C54/58/64
tCLCX
Vcc -- 0.5V 0.45V
0.7Vcc 0.2Vcc -- 0.1
tCHCX
tCHCL tCLCL
tCLCH
Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Mode (tCLCH=tCHCL=5 ns)
AC CHARACTERISTICS
(Ta=0C to 70C; VCC=5V+10%; VSS=0V; C1 for port 0, ALE and PSEN Outputs=100pF; C1 for other outputs=80pF)
EXTERNAL MEMORY CHARACTERISTICS
24 MHz Clock Min Max -- -- 68 -- 26 -- 31 -- -- 147 31 -- 110 -- -- 105 0 -- -- 37 -- 188 -- 10 230 -- 230 -- -- 157 0 -- -- 78 -- 282 -- 323 105 145 146 -- 26 -- 31 -- -- 0 26 57 40 MHz Clock Min Max ---- 35 -- 10 -- 15 -- -- 80 15 -- 60 -- -- 55 0 -- -- 20 -- 105 -- 10 130 -- 130 -- -- 90 0 -- -- 45 -- 165 -- 190 55 95 80 -- 10 -- 15 -- -- 0 10 40 Variable Oscillator (3.5 - 40 MHz) Min Max 3.5 40 2tCLCL-15 -- tCLCL-15 -- tCLCL-10 -- -- 4tCLCL-20 tCLCL-10 -- 3tCLCL-15 -- -- 3tCLCL-20 0 -- -- tCLCL-5 -- 5tCLCL-20 -- 10 6tCLCL-20 -- 6tCLCL-20 -- -- 4tCLCL-10 0 -- -- 2tCLCL-5 -- 7tCLCL-10 -- 8tCLCL-10 3tCLCL-20 3tCLCL+20 4tCLCL-20 -- tCLCL-15 -- tCLCL-10 -- -- 0 tCLCL-15 tCLCL+15
Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH
Parameter Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instr in ALE low to PSEN low PSEN pulse width PSEN low to valid instr in Input instr hold after PSEN Input instr float after PSEN Address to valid instr in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address to RD or WR low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Integrated Circuit Solution Inc.
MC009-0B
15
IC89C54/58/64
SERIAL PORT TIMING: SHIFT REGISTER MODE
24 MHz Clock Min Max 490 406 73 0 -- 510 -- -- -- 417 40 MHz Clock Min Max 290 310 240 -- 40 0 -- -- -- 250 Variable Oscillator (3.5-40 MHz) Min Max 12tCLCL-10 10tCLCL-10 2tCLCL-10 0 -- 12tCLCL+10 -- -- -- 10tCLCL
Symbol tXLXL tQVXH tXHQX tXHDX tXHDV
Parameter Serial port clock cycle time Output data setup to clock rising edg1 Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid
Unit ns ns ns ns ns
EXTERNAL CLOCK DRIVE CHARACTERISTICS
Symbol 1/tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency High time Low time Rise time Fall time Min 3.5 10 10 -- -- Max 40 -- -- 10 10 Unit MHz ns ns ns ns
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Integrated Circuit Solution Inc.
MC009-0B
IC89C54/58/64
Flash Program/Erase and Verification Characteristics Symbol Vpph Vppl Ipph Ippl tWSCV tCVQV tAVQV tCVPL tSHPL tAVPL tDVPL tPLBL tPLTL tBLCX tBLAX tBLPH tBLDX tBLBH tBLTH tBHSL tAXQX tCXQX tBLBHE tBLBHE1 tBLBHE2 tBLBHE3 tBLBHE4 tBLTHE tBLTHE1 tBLTHE2 tBLTHE3 tBLTHE4 Parameter Programming and Erase Enable Voltage Programming and Erase Enable Voltage Programming and Erase Enable Current while VPP=Vpph Programming and Erase Enable Current while VPP=Vppl Power Setup to Command Setup Low Command Valid to Data Output Valid Address Valid to Data Output Valid Command Valid to PROG# Low VPP Setup to PROG# Low Address Setup to PROG# Low Data Setup to PROG# Low PROG# Low to Busy# Low PROG# Low to Timeout Low Command Hold after Busy# Low Address Hold after Busy# Low Busy# Low to PROG# high Data Hold after Busy# Low Busy# Low to Busy# High Busy# Low to Timeout High VPP Hold after Busy# High Output Hold after Address Release Output Hold after Command Release Busy# Time while Chip Erase Busy# Time while Block 1 Erase (IC89C54) Busy# Time while Block 1 Erase (IC89C58) Busy# Time while Block 1 Erase (IC89C64) Busy# Time while Block 2 Erase (IC89C64) Busy# Low to Timeout High while Chip Erase Busy# Low to Timeout High while Block 1 Erase (IC89C54) Busy# Low to Timeout High while Block 1 Erase (IC89C58) Busy# Low to Timeout High while Block 1 Erase (IC89C64) Busy# Low to Timeout High while Block 2 Erase (IC89C64) Min 11.5 4.5 10 30 30 30 30 1 30 30 30 30 15 180 1 0 0 0.00018 0.00018 0.00018 0.00018 0.00018 Max 12.5 6.0 2.0 1.0 60 60 10 30 480 720 4.5 1.2 2.4 4.0 0.7 6.75 1.8 3.6 6.0 1.05 Unit V V mA mA ms ns ns ns ns ns ns us ns ns ns ns us us us us ns ns Sec Sec Sec Sec Sec Sec Sec Sec Sec Sec
Integrated Circuit Solution Inc.
MC009-0B
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IC89C54/58/64
TIMING WAVEFORMS
tLHLL
ALE
tLLPL tAVLL tPLPH tPLIV tPLAZ tPXIZ
A7-A0
PSEN
tLLAX tPXIX
INSTR IN
PORT 0
A7-A0
tLLIV tAVIV
PORT 2
A15-A8
A15-A8
Figure 11. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL tAVLL tRLAZ tLLAX
tRLRH tRHDZ tRHDX
DATA IN A7-A0 FROM PCL INSTR IN
RD PORT 0
tRLDV
A7-A0 FROM RI OR DPL
tAVWL tAVDV
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 12. External Data Memory Read Cycle
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Integrated Circuit Solution Inc.
MC009-0B
IC89C54/58/64
ALE
tWHLH
PSEN
tLLWL tWLWH tWHQX
A7-A0 FROM PCL INSTR IN
WR PORT 0
tAVLL tLLAX
A7-A0 FROM RI OR DPL
tQVWX
DATA OUT
tAVWL
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 13. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tQVXH tXHQX 0 tXHDV 1 2 tXHDX
VALID
DATAOUT DATAIN
3
4
5
6
7
SET TI
VALID
VALID
VALID
VALID
VALID
VALID
VALID SET RI
Figure 14. Shift Register Mode Timing Waveform
Integrated Circuit Solution Inc.
MC009-0B
19
IC89C54/58/64
P3[7:6] P2[7:6]
tCVQV
00H
P3[3:2] P2[5:0] P1[7:0] P0[7-0]
30H
31H
32H
tAVQV
D5H
tAVQV
tAVQV
05H/FFH
04H/08H/10H
VPP
tWSCV
PROG VCC
Figure 15. Read Signature bytes Timing(Arming Command)
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Integrated Circuit Solution Inc.
MC009-0B
IC89C54/58/64
P3[7:6] P2[7:6] P3[3:2] P2[5:0] P1[7:0] PROG
tDVPL
0EH(1)
0CH/0DH(2)
tCVPL
Valid Address(3)
tBLCX
tSLCV tCQCV
tCXQX
Valid Address(3)
tAVPL tBLPH
tBLAX
tAVQV
tAXQX
tBLDX
Valid Data(4) Valid Data
P0[7-0] P3.4(BUSY)
tSHPL
tPLBL
tBLBH tBHSL
VPP
tPLTL tBLTH
P3.5
1. 0EH is for code memory programming. In lock bits programming, 0FH, 03H, 05H, respect to lock bits 1, 2, 3. 2. 0CH is for code memory verification and 0DH is for concurrent memory verification. 09H is for Lock bits verification. 3. Address don't care while lock bits' programming or verification. 4. Data don't care while lock bits' programming.
Figure 16. Programming Timing
Integrated Circuit Solution Inc.
MC009-0B
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IC89C54/58/64
P3[7:6] P2[7:6] P3[3:2] P2[5:0] P1[7:0]
tCVPL
01H/02H/04H(1)
0CH/0DH(2)
tBLCX
tSLCV tCQCV
tCXQX
Valid Address(3)
tBLPH
tAVQV
tAXQX
PROG
P0[7-0]
tPLBL
Valid Data
P3.4(BUSY)
tSHPL
tBLBHE tBLBHEn tBHSL
VPP
tPLTL
P3.5
tBLTHE tBLTHEn
1. 01H/02H/04H are for Chip Erase/Block 1 Erase/Block 2 Erase. 2. 0CH is for code memory verification and 0DH is for concurrent memory verification. 09H is for Lock bits verification.
Figure 17. Erasing Timing
22
Integrated Circuit Solution Inc.
MC009-0B
IC89C54/58/64
tSLSH
1st stage test mode enable
2rd stage test mode enable
P2.6
tCVSL tPHCH
89H 59H 89H 59H
P0[7-0]
1. EA#, PROG#, P3.7, P2.7 are high level; P3.6 is low level.
Figure 18. Test Mode Entering Timing
tCLCX
Vcc -- 0.5V 0.45V
0.7Vcc 0.2Vcc -- 0.1
tCHCX
tCHCL tCLCL
tCLCH
Figure 19. External Clock Drive Waveform
Vcc - 0.5V 0.45V
0.2Vcc + 0.9V 0.2Vcc - 0.1V
Figure 20. AC Test Point Note: 1.AC inputs during testing are driven at Vcc-0.5v for logic "1" and 0.45V for logic "0". Timing measurements are made at Vih min for logic "1" and max for logic "0".
Integrated Circuit Solution Inc.
MC009-0B
23
IC89C54/58/64
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed 12 MHz Order Part Number IC89C54/58/64-12PL IC89C54/58/64-12W IC89C54/58/64-12PQ IC89C54/58/64-24PL IC89C54/58/64-24W IC89C54/58/64-24PQ IC89C54/58/64-40PL IC89C54/58/64-40W IC89C54/58/64-40PQ Package PLCC 600mil DIP PQFP PLCC 600mil DIP PQFP PLCC 600mil DIP PQFP
24 MHz
40 MHz
Integrated Circuit Solution Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
24 Integrated Circuit Solution Inc.
MC009-0B

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